The present invention relates in general to semiconductor integrated circuit devices and to a method for manufacturing such semiconductor integrated circuit devices; and, more particularly, the invention relates to a technique that is effective applied to a semiconductor integrated circuit device provided with two or more MISFET""s (Metal Insulator Semiconductor Field Effect Transistor) having gate insulation films that are different in film thickness on the same semiconductor substrate.
In the field of semiconductor device technology, a so-called two-type gate process, in which a gate insulation film having a thin film thickness and a gate insulation film having a thick film thickness are formed in the same semiconductor chip, has been used in practice concomitantly with the popularization of a semiconductor chip having multi-power sources.
For example, Japanese Published Unexamined Patent Application No. 2000-188338 discloses a two-type gate process in which a gate insulation film comprised of silicon oxide and a gate insulation film comprised of silicon nitride are formed on a first region and a second region of a semiconductor substrate, respectively.
In the two-type gate process described in the above-mentioned Patent Application, at first, a first silicon oxide film is formed on first and second regions of a semiconductor substrate, and then the first silicon oxide film on the first region is removed selectively by etching to expose the first region of the semiconductor substrate surface.
Next, a silicon nitride film is formed on the first region of the semiconductor substrate and on the first silicon oxide film on the second region, and then the second silicon nitride film and the first silicon oxide film are removed selectively by etching to expose the second region of the semiconductor substrate surface.
Next, the semiconductor substrate is subjected to thermal oxidation to form a second silicon oxide film on the second region of the semiconductor substrate surface. Thereby, the first gate insulation film comprised of silicon nitride is formed on the first region of the semiconductor substrate surface and the second gate insulation film comprised of silicon oxide is formed on the second region of the semiconductor substrate surface.
A thinner gate insulation film is required in proportion to the miniaturization of a MISFET in order to realize a low voltage operation of the MISFET. For example, a gate insulation film having a film thickness converted to that of a silicon film as thin as about 3 nm is required for a MISFET having a gate length of 0.2 xcexcm or shorter. However, a gate insulation film having a film thickness of 3 nm or thinner, consisting of silicon oxide, causes an increased direct tunnel current that flows through the gate insulation film, and the gate leakage current is significantly too large to ignore from the view point of reduction in power consumption.
To solve the above-mentioned problems, a countermeasure could be adopted in which a high dielectric film, such as a titanium oxide (TiO2) or tantalum oxide (Ta2O5) film having a relative dielectric constant larger than that of silicon oxide is used, to thereby increase the physical film thickness of a gate insulation film. Herein, it is required essentially to employ a process in which a part of a gate insulation film is formed of a high dielectric film, and the other part is formed of a silicon oxide film in the above-mentioned two-type gate process.
Furthermore, in the conventional gate forming process, in which a gate insulation film is formed of a silicon oxide film, when a gate electrode is formed by means of dry etching using a photoresist film as a mask, a semiconductor substrate is subjected to thermal oxidation, namely light oxidation, just after the gate electrode is formed, so as to improve the low withstand voltage of the gate electrode due to an undercut arising from isotropic etching of the gate oxide film of the sidewall end of the gate electrode. (For example, see Japanese Published Unexamined Patent Application No. Hei 7(1995)-94716).
However, when the gate insulation film formed of a high dielectric film is subjected to light oxidation after the gate electrode has been formed, the interface between the high dielectric film and the semiconductor substrate is oxidized and a silicon oxide film is formed. As a result, the dielectric constant of the gate insulation film decreases, and this decrease causes a problem. Therefore, it is not possible to improve the profile of the gate electrode sidewall end by means of light oxidation in this case.
It is an object of the present invention to provide a two-type gate process in which a gate insulation film is partially formed of a high dielectric film.
It is another object of the present invention to provide a technique for securing the reliability of ad MISFET having a gate insulation film formed of a high dielectric substance.
The above-mentioned and other objects and novel features of the present invention will be apparent from the following description and the attached drawings.
An outline of typical aspects of the invention disclosed in the present application will be described hereunder.
A method of manufacturing a semiconductor circuit device of the present invention includes the steps of: (a) forming a first insulation film having a relative dielectric constant higher than that of silicon nitride on the main surface of a semiconductor substrate followed by forming an oxidation prevention film on the first insulation film; (b) covering the oxidation prevention film on a first region of the semiconductor substrate, and etching the oxidation prevention film and the first insulation film on a second region of the semiconductor substrate, to thereby expose the semiconductor substrate surface of the second region; (c) after step (b), subjecting the semiconductor substrate to thermal oxidation to thereby form a second insulation film consisting of silicon oxide on the semiconductor substrate surface of the second region; and (d) forming a gate electrode of a first MISFET on the first insulation film of the first region and a gate electrode of a second MISFET on the second insulation film of the second region, after the oxidation prevention film on the first region is removed.
The method of manufacturing a semiconductor integrated circuit device of the present invention additionally includes the step (e) of thinning the respective gate electrodes of the first and second MISFET""s to thereby narrow the width of the gate electrode to a width narrower than that of the gate insulation film located under the gate electrode after the step (d).
A semiconductor integrated circuit device of the present invention has a first MISFET on a first region of the main surface of a semiconductor substrate and a second MISFET on a second region of the main surface of the semiconductor substrate, wherein a gate insulation film of the first MISFET comprises a first insulation film having a relative dielectric constant higher than that of silicon nitride, wherein a gate insulation film of the second MISFET comprises a second insulation film consisting of silicon oxide, and wherein the film thickness converted to that of a silicon oxide film of the first insulation film is thinner than the film thickness converted to that of a silicon oxide film of the second insulation film.
In the semiconductor integrated circuit device of the present invention, the film thickness converted to that of a silicon oxide film of the first insulation film is thinner than 3 nm, and the film thickness converted to that of a silicon oxide film of the second insulation film is equal to or thicker than 3 nm.
In the semiconductor integrated circuit device of the present invention, the first insulation film consists of an oxide of a 4A group element.
In the semiconductor integrated circuit device of the present invention, a sidewall spacer comprising a silicon nitride film or silicon oxide film and a silicon nitride film that covers the sidewall spacer are formed on the sidewall of a gate electrode of the first MISFET.